Creating a Project with the Terasic DE0-Nano FPGA Development Board

The DE0-Nano is one of the most popular development boards due to its low price (less than $100) and the Altera Cyclone IV FPGA, a low-cost, low-power device that provides more than 22K logic elements.

The board features:

- 2 x 20-pin headers, providing a total of 72 GPIO pins, two +5V pins, two +3V3 pins and four GND pins.

- 1 x 26-pin header, providing 18 GPIO pins and 8 pins for analog input.

- 1 x  12-bit ADC

- 1 x 2Kb EEPROM

- 1 x Accelerometer

Fig 1. Terasic DE0-Nano FPGA board

Terasic also provides software with a Control Panel and a System Builder. The Control Panel allows you to communicate with the board using your computer. Unfortunately, I was unable to make the program run in two different computers, so I won't be including it in my tutorials. The System Builder simply creates some basic files to help you starting a project: a QPF file (Quartus II project file), a Verilog file (declaring all I/O), a QSF file (FPGA pin assignment), a SDC file (timing constraints for testing) and an HTML file to view the descriptions of the I/Os.

Fig 2. DE0-Nano device layout

Most of the information in this tutorial can be found in far more detail in Terasic’s website in the Resources tab.

Here are the steps to create a project from scratch:

1. PREPARING THE SOFTWARE

1.1. Altera Software

Unless you have access to a paid license, we will be using the Web Edition of Altera Quartus II. This HDL analysis and synthesis tool provides compilation, timing analysis, RTL diagrams and simulation, among other features. The second tool that we want to install is ModelSim,  a simulation tool.

Fig 3. Altera Quartus II main window

You can download Quartus II v15.0 and ModelSim in Altera's website. 

1.2. Terasic Software

While it is possible to start a project without the software provided by Terasic, I recommend copying it to your computer since it provides the manuals, a few sample projects and the System Builder. 

If you don’t have the CD-ROM that came with the board, you can download the contents from this link.

1.3. Altera USB Blaster

In order to interface our DE0-Nano with our computer, we need to install its respective driver. Fortunately, no downloads are necessary if you already installed Quartus II.

To install the driver:

- Connect the DE0-Nano to your computer using a mini-USB cable.

- Go to Start Menu, type “Device Manager” and click on it once it appears under Control Panel.

- In the Device Manager, expand the Other Devices branch.

- Right-click on Unknown Device and click on Update Driver Software.

- Select “Browse my computer for driver software”, click on “Search for driver software in this location” and select the folder where Quartus II is installed. Make sure “Include subfolders” is marked.

2. CREATING YOUR FIRST PROJECT

2.1. System Builder

We need two files to start a project: The Quartus II project file (QPF) and the Settings File (QSF), which contains the PIN assignments, constraints, I/O settings and the pin timings.

Out of convenience, we are going to use the System Builder to create a Settings File specific to the DE0-Nano, the project file and template Verilog file:

- In the CD-ROM provided by Terasic, find the Tools folder, then the DE0_Nano_SystemBuilder folder and open DE0_Nano_SystemBuilder.exe

- In the System Builder, give a name to your project, select GPIO Default for both GPIO headers and give a prefix name for each header.

- Next, click on Generate and select a folder to place the new files.

Fig 4. Terasic DE0-Nano System Builder

2.2. Quartus II

- Open the QPF file that you created using the System Builder. This will open our project in Altera Quartus II.

- Click on the Project menu, then  Add/Remove Files in Project and click on the icon with the 3 dots (…)  

- Find the Verilog (.v) file created by the System Builder, click on Add and then OK.

The Verilog file should now appear in the Files window in Quartus II.

- Double click on the Verilog file to see the template for our project.

The Verilog file will have instantiations for all the FPGA pins available through the DE0-Nano board.

Fig 5. Adding files to project

Fig 6. Quartus II showing files in project

Since we want to create a simple project to test our board, we will delete the code in the Verilog file and paste the following code. 

NOTE: The top module must match the name of the project. I used Project1 in my example, so make sure that you change it accordingly. 

module Project1(        // The top-level module must match the name

input CLOCK_50,         // of the project file

output reg [7:0]LED

);

reg   [25:0]count;     

reg   clk2;

reg   state=0;

// clock divider 50MHz to 1Hz

always@(posedge CLOCK_50)

    begin

        if(count==26'd25_000_000)    // counts 25M clk cycles and

            begin                    // toggles clk2 hi or lo

             count<=0;               

             clk2 <= ~clk2;         

            end

        else

            begin

             count<=count+1;

            end

    end    

// state machine blinks on-board LEDs

always @(posedge clk2)

      begin

             case(state)

             1'b0:      begin

                  LED[7:0] <= 8'b01010101;

                  state <= 1'b1;

                  end

            1'b1:       begin

                  LED[7:0] = 8'b10101010;

                  state <= 1'b0;

                  end

            Default: begin

                  state <= 1'b0;

                  end

            endcase    

      end

endmodule

The code does two things. It creates a clock divider to create a 1Hz clock, and a state machine to make the on-board LEDs blink.

Note: If you do not want to copy and paste the code provided above, you can get a copy of my Project1.v Verilog file from my Github repository. Just make sure that you change the name of the file and the top-module to match the name of your project. All you need to do is add the file through the Projects menu.

2.3. Compiling the Design

- Once you Verilog file is ready, double-click on Compile Design. The compilation process should take a minute or two.

- Assuming there are no errors, double-click on EDA Netlist Writer.

- Finally, double-click on Program Device to open the Quartus II Programmer.

2.4. Configuring the FPGA

- In the Quartus II Programmer main window you should be able to see the SOF file for your project and the model number of your FPGA.

- In the top left, click on Hardware Setup and select “USB-Blaster” in the drop down menu. If you don’t see that option, read up section 1.3.

- Finally, press Start and the DE0-Nano should be configured.

Note: You are configuring the FPGA only. FPGAs are volatile devices, and will lose their configuration as soon as you power cycle it. To make your configuration permanent, you’ll have to create a file using Quartus II to configure the flash memory on the DE0-Nano.

Fig 7. Selecting programming hardware

Fig 8. Board programmed successfully

2.5. Test Code for the DE0-Nano

If you simply want to test your DE0-Nano board, here’s the SOF file that I created. Simply load it in the Quartus II Programmer (no need to open the compiler) and repeat section 2.4.