Finite State-Machine in Verilog - LED changing automatically

This is a code sample for a finite state-machine using Verilog and was tested using the Mojo FPGA board.

The code turns on one of the 8 LED in the Mojo board at a time. The LED transitions automatically at 1Hz.


Code Sample:

module LED_state_machine2(

    input   clk,         // 50MHz clock input   
    input   rst_n,       // input from reset button   
    input   cclk,        // clock input from AVR microcontroller
    output  reg[7:0]led, // output 8 onboard LEDs  
    
   // all connection below are for the microcontroller in Mojo

    output  spi_miso,          // SPI connections for AVR
    input   spi_ss,
    input   spi_mosi,
    input   spi_sck,
    output  [3:0] spi_channel, // AVR ADC channel select   
    input   avr_tx,            // AVR Tx => FPGA Rx
    output  avr_rx,            // AVR Rx => FPGA Tx
    input   avr_rx_busy        // AVR Rx buffer full
    );

// for Mojo only. these signals should be high-z when not used.

assign  spi_miso = 1'bz;
assign  avr_rx = 1'bz;
assign  spi_channel = 4'bzzzz;

wire    rst = ~rst_n; // make reset active high 
reg  [25:0] count;
reg         clk2;
reg   [2:0] state=0;


// clock divider 50MHz to 1Hz
always@(posedge clk)
    begin
        if(count==26'd25_000_000)    // counts 25M clk cycles and
            begin                    // toggles clk2 hi or lo
             count<=0;                
             clk2 <= ~clk2;          
            end
        else
            begin
             count<=count+1;
            end
    end    

// beginning of state-machine
always@(posedge clk2)  // state-machine change at clk2 transition
begin 
  if(rst)              // go to state 0 if rst is pressed
    state <= 3'd0;    
  else                 // otherwise start state-machine sequence
   begin             
    case(state)
     3'd0: begin
            led[7:0]<=8'b0000_0001;  // only led[0] is hi
            state <= 3'd1;           // jump to state 3'd1
           end
     3'd1: begin
            led[7:0]<=8'b0000_0010;  
            state <= 3'd2;           
           end            
     3'd2: begin
            led[7:0]<=8'b0000_0100;
            state <= 3'd3;
           end
     3'd3: begin
            led[7:0]<=8'b0000_1000;
            state <= 3'd4;
           end
     3'd4: begin
            led[7:0]<=8'b0001_0000;
            state <= 3'd5;
           end
     3'd5: begin
            led[7:0]<=8'b0010_0000;
            state <= 3'd6;
           end
     3'd6: begin
            led[7:0]<=8'b0100_0000;
            state <= 3'd7;
           end
     3'd7: begin
            led[7:0]<=8'b1000_0000; // back to state 0
            state <= 3'd0;          // volver a estado 0
           end
     default: state <= 3'b0; 
    endcase
   end
  end

endmodule