Clock Divider using Verilog

This is a code sample for a 50MHz to 5MHz clock divider using Verilog.

Note: This code will only work to divide the frequencies by an even number (2,4,10, etc).  For a frequency divider by odd numbers, visit this post.

Programmable logic devices (PLD) operate at relatively fast clock speeds. For instance, the clock in the Mojo FPGA runs at 50MHz. If we designed a circuit to make the on-board LEDs blink, they'd do so 50 or 25 million times per second (depending on the design) and therefore, the human eye wouldn't be able to catch it.

To solve that situation we can use the FPGA's input clock to create slower clock signals. The concept is simple. The circuit counts a certain number of clock cycles before setting the new signal as high or low. This new signal would then become our new slower clock.

The math to calculate the number of clk counts for certain frequencies is pretty straight forward:

   counter = (input_clock / new_clock) / 2

thus, if we want to create a 5MHz clock from 50MHz, our counter would use 5 input clock cycles:

   counter = (50MHz / 5MHz) / 2 = (10) / 2 = 5

In figure 1, we simulated our clock divider using Xilinx ISim to show the behavior of the input clock (clk), the counter (count) and the new clock (clk2). Notice that at every 5 clk cycles, clk2 toggles. The yellow tab shows that the count vector is at 5 (3'b101) and is followed by a clk2 transition.

Fig. 1. Behavioral simulation of 50MHz to 5MHz clock divider.

Code sample:

module clock_divider(
   input           clk,     // 50MHz clock input. reloj de 50MHz
   output reg      clk2,     // new 5MHz clock  
    );

reg [2:0] count;

// clock divider 50MHz to 5MHz
always@(posedge clk)
    begin
        if(count==3'd4)      // counts 5 clk cycles (0 thru 4)
            begin            
              count<=0;        
              clk2 <= ~clk2;   // toggles clk2 to hi or lo
            end
        else
            begin
              count<=count+1; 
            end              
    end